1. S.C Chang M. Marek-Sadowska, and T.T. Hwang, "Technology Mapping for TLU FPGAs Based on Decomposition of Binary Decision Diagrams," IEEE Transactions on Computer-Aided Design, Vol. 15, Issue 10, pp. 1226-1236, Oct. 1996.
2. S.C Chang M. Marek-Sadowska, and K.T. Cheng, "Perturb and Simplify: Multilevel Boolean Network Optimizer," IEEE Transactions on Computer-Aided Design, Vol. 15, Issue 12, pp. 1494-1504, Dec. 1996.
3. S.C Chang K.T. Cheng, N.S. Woo, and M. Marek-Sadowska, "Postlayout Logic Restructuring Using Alternative Wires," IEEE Transactions on Computer-Aided Design, Vol. 16, Issue 6, pp. 587-596, Jun. 1997.
4. S.C Chang and I.H. Cheng, "Efficient Boolean Division and Substitution Using Redundancy Addition and Removing," IEEE Transactions on Computer-Aided Design, Vol. 18, Issue 8, pp. 1096-1106, Aug. 1999.
5. S.C Chang L.V. Ginneken, and M. Marek-Sadowska, "Circuit Optimization by Rewiring," IEEE Transactions on Computer, Vol. 48, Issue 9, pp. 962-970, Sep. 1999.
6. S.C Chang W.B. Jone, and S.S. Chang, "TAIR: Testability Analysis by Implication Reasoning," IEEE Transactions on Computer-Aided Design, Vol. 19, Issue 1, pp. 152-160, Jan. 2000.
7. S.C Chang K.J. Lee, Z.Z. Wu, and W.B. Jone, "Reducing test application time by scan flip-flops sharing," IEEE Prpceedings Computers and Digital Techniques, Vol. 147, Issue 1, pp. 42-48, Jan. 2000.
8. J.C. Rau, W.B. Jone, S.C Chang and Y.L. Wu, "Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits," IEEE Prpceedings Computers and Digital Techniques, Vol. 147, Issue 5, pp. 343-348, Sep. 2000.
9. C.H. Cheng, W.B. Jone, S.C Chang and J.S. Wang, "Low-speed scan testing of charge-sharing faults for CMOS domino circuits," IEEE Electronics Letters, Vol. 36, Issue 20, pp. 1684-1685, Sep. 2000.
10. S.C Chang Z.Z. Wu, and S.H. Tu, "Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, pp. 3116-3124, 2001.
11. S.C Chang and J.C. Rau, "A Timing-Driven Pseudoexhaustive Testing for VLSI Circuits," IEEE Transactions on Computer-Aided Design, Vol. 20, Issue 1, pp. 147-158, Jan. 2001.
12. S.C Chang C.H. Cheng, W.B. Jone, S.D. Lee, and J.S. Wang, "Charge-Sharing Alleviation and Detection for CMOS Domino Circuits," IEEE Transactions on Computer-Aided Design, Vol. 20, Issue 2, pp. 266-280, Feb. 2001.
13. S.C Chang and Z.Z. Wu, "Theorems and Extensions of Single Wire Replacement," IEEE Transactions on Computer-Aided Design, Vol. 20, Issue 9, pp. 1159-1164, Sep. 2001.
14. C.H. Cheng, T.K. Tien, Y.C. Shen, and S.C Chang "Functional Slack Time Computation of Logic Gate," Journal of the Chinese Institute of Electrical Engineering, Vol. 8, pp. 325-334, Nov. 2001.
15. W.B. Jone, D.C. Huang, S.C Chang and S.R. Das, "Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis," VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Vol. 12, pp. 457-474, Dec. 2001.
16. S.C Chang K.Y. Chen, C.H. Cheng, W.B. Jone, and S.R. Das, "Random Pattern Testability Enhancement by Circuit Rewiring," VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Vol. 12, pp. 537-549, Dec. 2001.
17. Y.H. Su, C.H. Cheng, and S.C Chang "Novel Techniques for Improving Testability Analysis," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E85-A, pp. 2901-2912, 2002.
18. S.C Chang D.I. Cheng, and C.W. Yeh, "Removing Multiple Redundancies in Combinational Circuits," IEE Proceedings Computers and Digital Techniques, Vol. 149, Issue 1, pp. 1-8, Jan. 2002.
19. T.K. Tien, S.C Chang and T.K. Tsai, "Crosstalk Alleviation for Dynamic PLAs," IEEE Transactions on Computer-Aided Design, Vol. 21, Issue 12, pp. 1416-1424, Dec. 2002.
20. J.H. Jiang, W.B. Jone, S.C Chang and S. Ghosh, "Embedded Core Test Generation Using Broadcast Test Architecture and Netlist Scrambling," IEEE Transactions on Reliability, Vol. 52, Issue 4, pp. 435-443, Dec. 2003.
21. T.K. Tien, C.S. Tsai, S.C Chang and C.W. Yeh, "Power Minimization for Dynamic PLAs," IEEE Transactions on VLSI Systems, Vol. 14, Issue 6, pp. 616-624, Jun. 2006.
22. S.C Chang Z.Z. Wu, and H.Z. Yu, "Multiple Wire Reconnections Based on Implication Flow Graph," ACM Transactions on Design Automation of Electronic Systems, Vol. 11, pp. 939-952, Oct. 2006.
23. J.D. Hsieh, J.C. Lin, and S.C Chang "Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits," IEEE Transactions on Computer-Aided Design, Vol. 25, Issue 11, pp. 2341-2352, Nov. 2006.
24. C.H. Lin, C.T. Huang, C.P. Jiang, and S.C Chang "Optimization of Pattern Matching Circuits for Regular Expression on FPGA," IEEE Transactions on VLSI Systems, Vol. 15, Issue 12, pp. 1303-1310, Dec. 2007.
25. Y.S. Su, P.H. Chang, S.C Chang and T.T. Hwang, "Synthesis of a Novel Timing-Error Detection Architecture," ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Issue 1, Article 14, Jan. 2008.
26. Y.M. Kuo, Y.L. Chang, and S.C Chang "Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation," IEEE Transactions on Computer-Aided Design, Vol. 28, Issue 3, pp. 417-425, March 2009.
27. Y.M. Kuo, Y.T. Chang, S.C Chang and M. Marek-Sadowska, "Spare Cells with Constant Insertion for Engineering Change," IEEE Transactions on Computer-Aided Design, Vol. 28, Issue 3, pp. 456-460, March 2009.
28. D.S. Chiou, S.H. Chen, and S.C Chang "Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing," IEEE Transactions on VLSI Systems, Vol. 17, Issue 9, pp. 1330-1334, Sept. 2009.
29. D.C. Juan, Y.T. Chen, M.C. Lee, and S.C Chang "An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power-Gating Designs," IEEE Transactions on VLSI Systems, Vol. 18, Issue 2, pp. 246-255, Feb. 2010.
30. D.S. Chiou, Y.T. Chen, D.C. Juan, and S.C Chang "Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation," IEEE Transactions on Coumputer-Aided Design, Vol. 29, Issue 8, pp. 1285-1289, Aug. 2010.
31. Y.S. Su, W.K. Hon, C.C. Yang, S.C Chang and Y.J. Chang, "Clock Skew Minimization in Multi-Voltage Mode Designs using Adjustable Delay Buffers," IEEE Transactions on Coumputer-Aided Design of Integrated Circuits and Systems, Vol.29, Issue 12, pp.1921-1930, Dec. 2010.
32. C.H. Lin and S.C Chang "Efficient Pattern Matching Algorithm for Memory Architecture," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, Issue 1, pp. 33 - 41, Jan. 2011.
33. Y.S. Su, D.C. Wang, S.C Chang and M. Marek-Sadowska, "Performance Optimization Using Variable-Latency Design Style," IEEE Transactions on Very Large Scale Integration Systems, Vol.19, Issue, 10, pp.1874-1883, Oct. 2011.
34. C.L. Lung, H.C. Chang, D.M. Kwai, and S.C Chang "Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization," Information and Communications Research Laboratories Journal 141th, pp19-27, Oct. 2011.
35. Y.S. Su, C.L. Lung, and S.C Chang "TSV Fault-tolerant Unit for 3-D Clock Network," Information and Communications Research Laboratories Journal 141th, pp. 28-35, Oct. 2011.
36. S.H. Weng, Y.M. Kuo and S.C Chang, "Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic," ACM Transactions on Design Automation of Electronic Systems(TODAES), Vol. 17, Issue 2, April 2012.
37. M.C. Lee, Yiyu Shi, and S.C Chang, "Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs," IEEE Transactions on Coumputer-Aided Design of Integrated Circuits and Systems, Vol.31, Issue 7, pp.1041-1049, July 2012.
38. C.L. Lung, Y.S. Su, S.H. Huang, Y. Shi, and S.C Chang, "Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs," IEEE Transactions on Coumputer-Aided Design of Integrated Circuits and Systems, Vol.32, Issue 7, pp.1100-1109, July 2013.
39. C.L. Lung, Y.C. Chen, J.H. Chien, and S.C Chang, "Design and Investigation of TSV Fault-tolerant Mechanisms," in Information and Communications Research Laboratories Journal, Vol. 148, pp. 48-55, Dec. 2012.
40. J.S. Wang, K.J. Chang, C.Yeh, and S.C Chang, "Embedding Repeaters in Silicon IPs for Cross-IP Interconnections," in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, Issue 3, pp.597-601, Mar. 2013.
41. WT Chen, YL Lin, CY Lee, JL Chiang, MF Chang, and S.C Chang, "Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan," in IEEE Access, Vol.1, pp.123-130, May. 2013.
42. C Lin, C Liu, L Chien, and S.C Chang, "Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs," in IEEE Transactions on Computers (TC), Vol.62, Issue 10, pp.1906-1916, Oct. 2013.
43. Y.G. Chen, Geng H, K. Y. Lai, Yiyu Shi, and S.C Chang, "Multi-Bit Retention Registers for Power Gated Designs: Concept, Design and Deployment," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.33, Issue 4, pp.507-518, Mar. 2014.
44. Cody H. Yu, C.C. Lung, Y.L. Ho, R.S. Hsu, D.M. Kwai, and S.C Chang, "Thermal-Aware On-Line Scheduler for 3D Many-Core Processor Throughput Optimization," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.33, Issue 5, pp.763-773, May. 2014.
45. W.Y. Wen, J.C. Li, S.Y. Lin, J.Y. Chen, and S.C Chang, "A Fuzzy-Matching Model with Grid Reduction for Lithography Hotspot Detection," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.33, Issue 11, pp.1671-1680, Nov. 2014.
46. Y.G. Chen, W.Y. Wen, Yiyu Shi, W.K. Hon, and S.C Chang, "Novel Spare TSV Deployment for 3D ICs Considering Yield and Timing Constraints," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.34, Issue 4, pp. 577-588, Mar. 2015.
47. Mac Y.C. Kao, K.T. Tsai, and S.C Chang, "A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning," in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.23, Issue 7, pp.1210-1220, Jul. 2015.
48. H.M. Chou, M.Y. Hsiao, Y.C. Chen, K.H. Yang, Jean Tsao, C.L. Lung, S.C Chang, W.B. Jone and T.F Chen, "Soft-Error-Tolerant Design Methodology for Balancing Performance, Power and Reliability," in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.23, Issue 9, pp. 1628-1639, Sep. 2015.
49. H.M. Chou, Y. C. Chen, J. Tsao, K. H. Yang, S.C. Chang, W. B. Jone, and T. F. Chen, "High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols," in IEEE Transactions Very Large Scale Integration Systems (TVLSI), Vol.24, Issue 3, pp.1169-1173, Mar. 2016.
50. C.H. Chou, H.H. Yeh, S.H. Huang, Y.T. Nieh, S.C. Chang, and Y.T. Chang, "Skew Minimization with Low Power for Wide-Voltage-Range Multi-Power-Mode Designs," in IEEE Transactions Very Large Scale Integration Systems (TVLSI), Vol.24, Issue 3, pp.1189-1192, Mar. 2016.
51. C.H. Chou, Y.T. Lai, Y.C. Chang, C.Y. Wang, L.C. Cheng, S.H. Huang and S.C. Chang, "Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.36, Issue 1, pp.146-155, Jan. 2017.
52. Y.C. Peng, C.C. Chen, H.J. Tsai, K.H. Yang, P.Z. Huang, S.C. Chang, W.B. Jone, T.F. Chen, "Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control," in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.22, Issue 3, pp.46, Mar. 2017.
53. C.H. Lin, J.C. Li, C.H. Liu and S.C. Chang, "Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units," in IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.28, Issue 9, pp.2639-2650, Sept. 2017.
54. Cheng-Hung Lin, Sze-Chen Cho, and S.C Chang, "An Adaptive Mechanism for Designing Efficient Snoop Filters," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.26, Issue 7, pp.1233-1240, Mar. 2018.
55. Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, S.C. Chang, "Sensor-Based Time Speculation in the Presence of Timing Variability," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol.37, Issue 6, pp.1133-1142, Jun. 2018.
56. Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee and S.C Chang, "Contactless Testing for Prebond Interposers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1005-1014, June. 2018.
57. Yi-Wen Hung, Yung-Chih Chen, Chi Lo, Austin Go So and Shih-Chieh Chang, "Dynamic Workload Allocation for Edge Computing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.519-529, March. 2021.

(B) Conference Publications

1. S.C Chang and M. Marek-Sadowska, "Technology Mapping via Transformation of Function Graphs," in Proc. of International Conference on Computer Design(ICCD), pp. 159-162, Oct. 1992.
2. S.C Chang and M. Marek-Sadowska, "Technology Mapping and Circuit Depth Optimization for Field Programmable Gate Arrays," in Proc. of Custom Integrated Circuits Conference(CICC), pp. 3.5.1-3.5.4, May 1993.
3. S.C Chang and M. Marek-Sadowska, "BDD Representation of Incompletely Specified Functions," in Proc. of International Workshop on Logic Synthesis, pp. P6c-1-P6c-5, 1993.
4. D.I. Cheng, S.C Chang and M. Marek-Sadowska, "Partitioning Combinational Circuits in Graph and Logic Domains," in Proc. of Workshop on Synthesis and Systems Integration of Mixed Information Technologies(SASIMI), pp. 404-412, 1993.
5. S.C Chang D.I. Cheng, and M. Marek-Sadowska, "Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions," in Proc. of European Design and Test Conference(EDTC), pp. 620-624, March 1994.
6. S.C Chang K.T. Cheng, N.S. Woo, and M. Marek-Sadowska, "Layout Driven Logic Synthesis for FPGAs," in Proc. of Design Automation Conference(DAC), pp. 308-313, June 1994.
7. S.C Chang and M. Marek-Sadowska, "Perturb and Simplify: Multi-level Boolean Network Optimizer," in Proc. of International Symposium on Circuits and Systems(ISCAS), pp. 2-5, Nov. 1994.
8. C.C. Lin, K.C. Chen, S.C Chang M. Marek-Sadowska, and K.T. Cheng, "Logic Synthesis for Engineering Change," in Proc. of Design Automation Conference(DAC), pp. 647-652, June 1995.
9. S.C Chang M. Marek-Sadowska, and K.T. Cheng, "An Efficient Algorithm for Local Don't Care Sets Calculation," in Proc. of Design Automation Conference(DAC), pp. 663-667, June 1995.
10. S.C Chang and M. Marek-Sadowska, "Perturb and Simplify: Optimizing Circuits with External Don't Cares," in Proc. of European Design and Test Conference(EDTC), pp. 402-406, March 1996.
11. S.C Chang L.P.P.P.V. Ginneken, and M. Marek-Sadowska, "Fast Boolean Optimization by Rewiring," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 262-269, Nov. 1996.
12. S.C Chang D.I. Cheng, and C.W. Yeh, "On Removing Multiple Redundancies in Combinational Circuits," in Proc. of Design, Automation and Test in Europe(DATE), pp. 738-742, Feb. 1998.
13. S.C Chang and D.I. Cheng, "Efficient Boolean Division and Substitution," in Proc. of Design Automation Conference(DAC), pp. 342-347, June 1998.
14. W.B. Jone, J.C. Rau, S.C Chang and Y.L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI circuits," in Proc. of International Test Conference(ITC), pp. 322-330, Oct. 1998.
15. S.C Chang S.S. Chang, W.B. Jone, and C.C. Tsai, "A Novel Combinational Testability Analysis by Considering Signal Correlation," in Proc. of International Test Conference(ITC), pp. 658-667, Oct. 1998.
16. S.C Chang K.Y. Chen, W.B. Jone, and S.R. Das, "Random Pattern Testability Enhancement by Circuit Rewiring," in Proc. of International Conference on VLSI Design, 1999.
17. C.W. Yeh, M.C. Chang, S.C Chang and W.B. Jone, "Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications," in Proc. of Design Automation Conference(DAC), pp. 68-71, Jun. 1999.
18. C.H. Cheng, S.C Chang J.S. Wang, and W.B. Jone, "Charge Sharing Fault Detection for CMOS Domino Logic Circuits," in Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 77-85, Nov. 1999.
19. C.W. Yeh, M.C. Chang, S.C Chang and W.B. Jone, "Power Reduction Through Iterative Gate Sizing and Voltage Scaling," in Proc. of International Symposium on Circuits and Systems(ISCAS), pp. 246-249, July 1999.
20. S.C Chang J.C. Chuang, and Z.Z. Wu, "Synthesis for Multiple Input Wires Replacement of a Gate for Wiring Consideration," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 115-118, Nov. 1999.
21. S.C Chang and J.C. Rau, "A Timing-Driven Pseudo-Exhaustive Testing of VLSI Circuits," in Proc. of International Symposium on Circuits and Systems(ISCAS), pp. 665-668, May 2000.
22. J.C. Rau, Y.M. Chen, and S.C Chang "A Compact Factored Form for a Boolean Function," in Proc. of International Symposium on Circuits and Systems(ISCAS), pp. 317-320, May 2000.
23. C.H. Cheng, S.C Chang J.S. Wang, and W.B. Jone, "Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits," in Proc. of Latin-American Test Workshop , pp. 59-64, 2000.
24. C.H. Cheng, J.S. Wang, S.C Chang and W.B. Jone, "Scan-Resistant Charge-Sharing Fault in Domino Circuit," in Proc. of Computer Society Annual Workshop on VLSI, 2000.
25. C.H. Cheng, S.C Chang S.D. Li, W.B. Jone, and J.S. Wang, "Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 387-340, Nov. 2000.
26. S.C Chang Z.Z. Wu, and H.Z. Yu, "Wire Reconnections Based on Implication Flow Graph," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 533-537, Nov. 2000.
27. Y.H. Su, C.H. Cheng, and S.C Chang "Novel Techniques for Improving Testability Analysis," in Proc. of Asia Test Symposium(ATS), pp. 392-397, Dec. 2000.
28. C.H. Cheng, W.B. Jone, J.S. Wang, and S.C Chang "Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits," in Proc. of Asia Test Symposium(ATS), pp. 435-440, Dec. 2000.
29. J.H. Jiang, W.B. Jone, and S.C Chang "Embedded Core Testing Using Broadcast Test Architecture," in Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 95-103, Oct. 2001.
30. J.C. Rau, J.H. Wang, and S.C Chang "Logic Optimization of Circuits with Pre-defined Internal Don't Cares," in Proc. of International Conference on Electronics, Circuits, and Systems, pp. 237-240, Sep. 2001.
31. T.K. Tien, S.C Chang and T.K. Tsai, "Crosstalk Alleviation for Dynamic PLAs," in Proc. of Design, Automation and Test in Europe(DATE), pp. 683-687, Mar. 2002.
32. S.C Chang C.T. Hsieh, and K.C. Wu, "Re-synthesis for Delay Variation Tolerance," in Proc. of Design Automation Conference(DAC), pp. 814-819, July 2004.
33. S. Ghosh, K.W. Lai, W.B. Jone, and S.C Chang "Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits," in Proc. of Asia Test Symposium(ATS), pp. 210-215, Nov.2004.
34. C.T. Hsieh, J.C. Lin, and S.C Chang "A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 537-540, Nov. 2004.
35. C.H. Lin, Y.C. Huang, S.C Chang and W.B. Jone, "Design and Design Automation of Rectification Logic for Engineering Change," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 1006-1009, Jan. 2005.
36. T.K. Tien, C.S. Tsai, S.C Chang and C.W. Yeh, "Power Minimization for Dynamic PLAs," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 1010-1013, Jan. 2005.
37. Y.F. Lin, S.Y. Huang, S.Y. Hsu, I.L. Chen, C.T. Hsieh, J.C. Lin, and S.C Chang "Power Estimation Starategies For A Low-Power Security Processor ," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 367-371, Jan. 2005.
38. Y.L. Huang, C.Y. Wang, R. Yeh, and S.C Chang "Language-Based High Level Transaction Extraction on On-chip Buses," in Proc. of International Symposium on Quality Electronic Design(ISQED), pp. 231-236, March 2006.
39. C.T. Hsieh, K.C. Wu, and S.C Chang "Delay Variation Tolerance for Domino Circuits," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 24-27, Jan. 2006.
40. C.H. Lin, C.T. Huang, C.P. Jiang, and S.C Chang "Optimization of Regular Expression Pattern Matching Circuits on FPGA," in Proc. of Design, Automation and Test in Europe(DATE), pp.1-6, March 2006.
41. Y.M. Kuo, Y.L. Chang, and S.C Chang "Efficient Boolean Characteristic Function for Fast Timed ATPG," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 96-99, Nov. 2006.
42. C.T. Hsieh, J.C. Lin, and S.C Chang "Efficient Transition-Mode Boolean Characteristic Function with its Application to Maximum Instantaneous Current Analysis," in Proc. of International Symposium on Quality Electronic Design(ISQED), pp. 602-606, March 2007.
43. Y.M. Kuo, C.H. Lin, C.Y. Wang, S.C Chang and P.H. Ho, "Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure," in Proc. of International Symposium on Quality Electronic Design(ISQED), pp. 344-349, March 2007.
44. Y.S. Su, D.C. Wang, S.C Chang and M. Marek-Sadowska, "An Efficient Mechanism for Performance Optimization of Variable-Latency Designs," in Proc. of Design Automation Conference(DAC), pp. 976-981, June 2007.
45. D.S. Chiou, D.C. Juan, Y.T. Chen, and S.C Chang "Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization," in Proc. of Design Automation Conference(DAC), pp. 81-86, June 2007.
46. D.S. Chiou, S.H. Chen, S.C Chang and C.W. Yeh, "Timing Driven Power Gating," in Proc. of Design Automation Conference(DAC), pp. 121-124, July 2006.
47. Y.T. Chen, D.C. Juan, M.C. Lee, and S.C Chang "An Efficient Wake-up Schedule during Power Mode Transition Considering Spurious Glitches Phenomenon," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 779-782, Nov. 2007.
48. Y.M. Kuo, Y.T. Chang, S.C Chang and M. Marek-Sadowska, "Engineering Change Using Spare Cells with Constant Insertion," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 544-547, Nov. 2007.
49. A. Todri, M. Marek-Sadowska, and S.C Chang "Analysis and Optimization of Power-Gated ICs with Multiple Power Gating Configurations," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 783-790, Nov. 2007.
50. D.S. Chiou, Y.T. Chen, D.C. Juan, and S.C Chang "Sleep Transistor Sizing in Power Gating Designs," Invited Paper of International Conference on ASIC(ASICON), pp. 1326-1331, Oct. 2007.
51. Cheng-Hung Lin, Yu-Tang Tai, and S.C Chang "Optimization of Pattern Matching Algorithm for Memory Based Architecture," in Proc. of Symposium on Architectures for Networking and Communications Systems(ANCS), pp. 11-16, Dec. 2007.
52. Y.S. Su, P.H. Chang, S.C Chang and T.T. Hwang, "Synthesis of a Novel Timing-Error Detection Architecture," in Proc. of IEEE International Symposium on VLSI Design, Automation and Test(VLSI-DAT), pp. 160-163, April 2008.
53. S.H. Weng, Y.M. Kuo, S.C Chang and M. Marek-Sadowska, "Timing Analysis Considering IR Drop Waveforms in Power Gating Designs," in Proc. of International Conference on Computer Design(ICCD), pp. 532-537, Oct. 2008.
54. Y.M. Kuo, S.H. Weng, and S.C Chang "A Novel Sequential Circuit Optimization with Clock Gating Logic," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 230-233, Nov. 2008.
55. M.C. Lee, S.C Chang C.S. Su, E. Tsai, "Performance and Wake-Up Schedule Optimization of Power Gating Design," in Proc. of International SoC Design Conference(ISOCC), Nov. 2008.
56. C.L. Hsieh, J. Cong, Z. Zhang, and S.C Chang "Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), March 2008.
57. M.C. Lee, Y.T. Chen, Y.T. Cheng, and S.C Chang "An Efficient Wakeup Scheduling Considering Resource Constraint for Sensor-Based Power Gating Designs," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 457-460, Nov. 2009.
58. Y.S. Su, W.K. Hon, C.C. Yang, S.C Chang and Y.J. Chang, "Value Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 535-538, Nov. 2009.
59. C.L. Lung, Z.Y. Zeng, C.H. Chou, and S.C Chang "Clock Skew Optimization Considering Complicated Power Modes," in Proc. of Design, Automation and Test in Europe(DATE), pp. 1474-1480, March 2010.
60. Y.C. Kao, H.M. Chou, K.T. Tsai, and S.C Chang "An Efficient Phase Detector Connection Structure for the Skew Synchronization System," in Proc. of Design Automation Conference(DAC), pp. 729-734, June 2010.
61. C.L. Lung, H.C. Hsiao, Z.Y. Zeng, and S.C Chang "LP-based multi-mode multi-corner clock skew optimization," in Proc. of International Symposium on VLSI Design Automation and Test(VLSI-DAT), pp. 335-338, April 2010.
62. C.L. Lung, Y.L. Ho, S.H. Huang, C.W. Hsu, J.L. Liao, S.Y. Huang, and S.C Chang "Thermal analysis experiences of a tri-core SoC system," in Proc. of International Conference on Green Circuits and Systems(ICGCS),pp. 589-594, June 2010.
63. Mac Y.C. Kao, H.M. Chou, K.T. Tsai, and S.C Chang "Synthesis of an Efficient Controlling Structure for Post-Silicon Clock Skew Minimization," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 746-749, Nov. 2010.
64. C.H. Lin, S.Y. Tsai, C.H. Liu, S.C Chang and Jyuo-Min Shyu, "Accelerating String Matching Using Multi-threaded Algorithm on GPU," in Proc. IEEE GLOBAL COMMUNICATIONS CONFERENCE (IEEE GLOBECOM 2010), Miami, Florida, USA, pp. 1-5, December 6-10, Dec. 2010.
65. M.C. Lee, Y.G. Chen, D.K.Huang, S.C Chang "NBTI-Aware Power Gating Design," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 609-614, Jan. 2011.
66. C.L. Lung, Y.L. Ho, D.M. Kwai, and S.C Chang "Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization," in Proc. of Design, Automation & Test in Europe(DATE), pp. 1-6, March 2011.
67. J.H. Chien, C.L. Lung, K.J. Tsai, C.C. Hsu, T.S. Chen, Y.F. Chou, P.H. Chen, S.C Chang and D.M. Kwai, "Realization of 3-dimentional virtual 126-core system with thermal sensor-network using metallic thermal skeletons," in Proc. of International Conference on Electronic Components and Technology Conference(ECTC), pp. 873-879, Lake Buena Vista, FL., USA., June 2011.
68. C.L. Lung, Y.S. Su, S.H. Huang, Yiyu Shi, and S.C Chang "Fault-Tolerant 3D Clock Network," in Proc. of Design Automation Conference(DAC), pp. 645-651, June 2011.
69. K.C. Wu, D. Marculescu, M.C. Lee, and S.C Chang "Analysis and Mitigation of NBTI-Induced Performance Degradation for Power-Gated Circuits," Prof. on the International Symposium on Low Power Electronics and Design(ISLPED), pp. 139 - 144, Aug. 2011.
70. J.H. Chien, C.L. Lung, T.W. Lin, K.J. Tsai, T.S. Chen, Y.F. Chou, P.H. Chen, S.C Chang and D.M. Kwai, "Design and implementation of 3D-thermal test chip for exploration of package effects," in Proc. of International Conference on Microsystems Packaging Assembly and Circuits Technology Conference(IMPACT), pp.238-241, Oct. 2011.
71. H.M. Chou, H. Yu, and S.C Chang "Useful-Skew Clock Optimization for Multi-Power Mode Designs," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 647-650, Nov. 2011.
72. Mac Y.C. Kao, K.T. Tsai, and S.C Chang "A Robust Architecture for Post-Silicon Skew Tuning," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 774-778, Nov. 2011.
73. C.H. Chou, N.Y. Tsai, H. Yu, C.R. Lee, Yiyu Shi and S.C Chang "On the Preconditioner of Conjugate Gradient Method - A Power Grid Simulation Perspective," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 494-497, Nov. 2011.
74. C.L. Lung, J.H. Chien, Yiyu Shi, and S.C Chang "TSV Fault-tolerant Mechanisms with Application to 3D Clock Networks," in Proc. of International SoC Design Conference(ISOCC), pp. 127-130, Nov. 2011.
75. C.H. Lin, C.H. Liu, and S.C Chang, "Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU," in Proc. of IEEE GLOBAL COMMUNICATIONS CONFERENCE (IEEE GLOBECOM 2011), Houston, Texas, USA, pp.1706-1710, Dec. 2011.
76. Mac Y.C. Kao, K.T. Tsai, H.M. Chou, and S.C Chang "Post Silicon Skew Tuning: Survey and Analysis," in Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 646-651, January 2012.
77. CH Lin, CH Liu, LS Chien, S.C Changand WK Hon, "PFAC Library: GPU-based string matching algorithm," in proc. of GPU Technology Conference (GTC 2012), San Jose, California, USA, May 2012.
78. K.C.Wu, M.C. Lee, D. Marculescu, and S.C Chang "Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms, " in Proc. of Design, Automation & Test in Europe Conference & Exhibition(DATE), pp. 1269-1274, March 2012.
79. H.Y. Lin, C.Y. Wang, S.C Chang Y.C. Chen, H.M. Chao, C.Y. Huang, Y.C. Yang, and C.C. Shen, "A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis," in Proc. of Design, Automation & Test in Europe Conference & Exhibition(DATE), pp. 147-152, March 2012.
80. M.C. Lee, Yiyu Shi, Y.G. Chen, D. Marculescu, and S.C Chang "Efficient On-line Module-Level Wake-Up Scheduling for High Performance Multi-Module Designs," in Proc. of International Symposium on Physical Design(ISPD), pp. 97-104, March 2012.
81. C.H. Lin, C.H. Liu, S.C Chang and W.K. Hon, "Memory-Efficient Pattern Matching Architectures Using Perfect Hashing on Graphic Processing Units, " in Proc. Annual IEEE International Conference on Computer Communications (IEEE INFOCOM), Orlando, Florida, USA,pp. 1978 - 1986, March 2012.
82. JH Chien, H Yu, NY Tsai, CL Lung, CC Hsu, YF Chou, PH Chen, S.C Changand DM Kwai, "Hybrid thermal solution for 3D-ICs: Using thermal TSVs with placement algorithm for stress relieving structures," in Proc. IEEE Electronic Components and Technology Conference (ECTC), pp. 1455-1460, May. 2012.
83. JH Chien, H Yu, CL Lung, HC Chang, NY Tsai, YF Chou, PH Chen, S.C Changand DM Kwai, "Efficient Thermal stress aware design for stacking IC with through glass via," in Proc. of International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp. 133-136, Oct. 2012.
84. Y.G. Chen, Yiyu Shi, K. Y. Lai, Geng H., and S.C Chang "Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms," in Proc. of International Conference on Computer Aided Design, ICCAD, pp. 309-316, Nov. 2012.
85. S.Y. Lin, J.Y. Chen, J.C. Li, W.Y. Wen, and S.C Chang "A novel fuzzy matching model for lithography hotspot detection," in Proc. of 50th Annual Design Automation Conference(DAC), pp. 1-6, June 2013.
86. W.P. Tu, C.H. Chou, S.H. Huang, S.C Chang Y.T. Nieh and C.Y. Chou, "Low-Power Timing Closure Methodology for Ultra-Low Voltage Designs," in Proc. of International Conference on Computer Aided Design(ICCAD), pp. 309-316, Nov. 2012.
87. J.H. Chien, H. Yu, C.-L. Lung, Y.-F. Chou, D.-M. Kwai, and S.C Chang, "IC-Package Co-design by Computational Thermographics," in Proc. of International Microsystems, Package, Assembly Conference Taiwan (IMPACT), pp. 170-171, Oct. 2013.
88. Y.G. Chen, K. Y. Lai, M.C. Lee, Yiyu Shi, WK Hon, and S.C Chang , "Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits," in proc. of Design, Automation and Test in Europe (DATE), pp. 1-4, Mar. 2014.
89. J.H. Chien, H. Yu, R.-S. Hsu, H.-J. Lin, and S.C Chang "Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images," in proc. of Design, Automation and Test in Europe (DATE), pp. 1-4, Mar. 2014.
90. H.M. Chou, H.C. Wu, Y.C. Chen, and S.C Chang , "Concurrency-oriented SoC re-certification by reusing block-level test vectors," in proc. of 15th International Symposium on of Quality Electronic Design (ISQED), pp.140-147, Mar. 2014.
91. Y.G. Chen, Tao Wang, K.Y. Lai, W.Y. Wen, Yiyu Shi, and S.C Chang "Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs," in proc. of 51th Annual Design Automation Conference (DAC), pp.1-6, Jun. 2014.
92. J.H. Chien, R.S. Hsu, H.J. Lin, K.Y. Yeh, and S.C Chang "Contactless Stacked-die Testing for Pre-bond Interposers," in proc. of 51th Annual Design Automation Conference (DAC) , pp.1-6, Jun. 2014.
93. H.M. Chou, H.C. Wu, Y.C. Chen, J. Tsao, and S.C Chang, "Hybrid Coverage Assertions for Efficient Coverage Analysis across Simulation and Emulation Environments," in proc. of 20th Asia and South Pacific Design Automation Conference (ASPDAC), pp.594-599, Jan. 2015.
94. Y.G. Chen, W.Y. Wen, Tao Wang, Yiyu Shi, and S.C Chang, "Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation," in proc. of 2015 International symposium on Physical Design (ISPD), pp.41-48, Mar. 2015.
95. J.H. Chien, N.T. Chang, C.H. Huang, S.C Chang, and W.H. Wang, "Cyber physical system (CPS) for contactless IC testing," in proc. of 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp.340-343, Oct. 2015.
96. Y.G. Chen, W.Y. Wen, Y.T. Wang, Y.L. Lee and S.C Chang, "A Novel Low-Cost Dynamic Logic Reconfigurable Structure Strategy for Low Power Optimization," in proc. of 21th Asia and South Pacific Design Automation Conference (ASPDAC), pp.250-255, Jan. 2016.
97. C.H. Chou, Z.Y. Wang, T.Y. Chang, S.H. Huang and S.C Chang, "2.5D System Synthesis Methodology under Performance, Power and Thermal Constraints," in Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, Apr. 2016.
98. Y.H. Ting, C.Y. Wang, Y.S. Chang, T.J. Lin, S.C Chang and J.S. Wang "Overoptimistic Voltage Scaling in Pre-error AVS Systems and Learning-based Alleviation," accepted by 29th IEEE International System-on-Chip Conference (SOCC), Sep. 2016.
99. Travis E. Schulze, Kevin Kwiat, Charles Kamhoua, S.C Chang and Yiyu Shi, "RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan," in Proc. of IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), pp.1-6, Dec. 2016.
100. Y.G. Chen, Michihiro Shintani, Takashi Sato, Yiyu shi and S.C Chang, "Pattern Based Runtime Voltage Emergency Prediction: An Instruction-Aware Block Sparse Compressed Sensing Approach," in Proc. of 22th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.543-548, Jan. 2017.
101. Kassan Unda, Chung-Han Chou, Cheng Zhuo, Yiyu Shi and S.C Chang, "CN-SIM: A cycle-accurate full system power delivery noise simulator," in Proc. of 22th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.554-559, Jan. 2017.
102. You-Luen Lee, Da-Cheng Juan, Xuan-An Tseng, Yu-Ting Chen and S.C Chang, "DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters," in Joint European Conference on Machine Learning and Knowledge Discovery in Databases, pp.64-76, Sep. 2017.
103. Chi Lo, Yu-Yi Su, Chun-Yi Lee and S.C Chang, "A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing," in 2017 IEEE 35th International Conference on Computer Design (ICCD), pp.273-280, Nov. 2017.
104. Xuan-An Tseng, Da-Cheng Juan, Chun-Hao Liu, Wei Wei, Yu-Ting Chen, Jia-Yu Pan and S.C Chang, "Nested LSTM: Modeling Taxonomy and Temporal Dynamics in Location-Based Social Network," in MiLeTS'18, August 2018, London, United Kingdom
105. Chi-Hung Hsu, Shu-Huan Chang, Da-Cheng Juan, Jia-Yu Pan, Yu-Ting Chen, Wei Wei and S.C Chang, "MONAS: Multi-Objective Neural Architecture Search using Reinforcement Learning," arXiv preprint arXiv:1806.10332
106. Xuan-An Tseng, Da-Cheng Juan, Chun-Hao Liu, Wei Wei, Yu-Ting Chen, Jia-Yu Pan and S.C Chang "Hierarchical LSTM: Modeling Temporal Dynamics and Taxonomy in Location-Based Mobile Check-Ins," in Proc. of 2019 Pacific-Asia Conference on Knowledge Discovery and Data Mining (PAKDD), pp. 217-228, Mar. 2019.
107. Hao-Yun Chen, Pei-Hsin Wang, Chun-Hao Liu, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan, "Complement Objective Training," in Seventh International Conference on Learning Representations (ICLR'19)
108. Hao-Yun Chen*, Jhao-Hong Liang*, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan, "Improving Adversarial Robustness via Guided Complement Entropy," in International Conference on Computer Vision (ICCV'19)
109. Chu-Chien Wei*, Li-Huang Tsai*, Hsin-Ping Chou, Shih-Chieh Chang, "Person Identification by Walking Gesture Using Skeleton Sequences," in Proc. of 2020 International Conference on Advanced Concepts for Intelligent Vision Systems (ACIVS), pp. 205-214, Feb. 2020.
110. Xiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen, Shih-Chieh Chang, "Accuracy Tolerant Neural Networks Under Aggressive Power Optimization," in Proc. of 2020 Design, Automation and Test in Europe (DATE), pp. 774-779, Mar. 2020.
111. Li-Huang Tsai, Shih-Chieh Chang, Yu-Ting Chen, Jia-Yu Pan, Wei Wei, Da-Cheng Juan, "Calibrated BatchNorm: Improving Robustness Against Noisy Weights in Neural Networks," arXiv preprint arXiv:2007.03230
112. Chieh-Yang Chen, Pei-Hsin Wang, Shih-Chieh Chang, Da-Cheng Juan, Wei Wei, Jia-Yu Pan, "AirConcierge: Generating Task-Oriented Dialogue via Efficient Large-Scale Knowledge Retrieval," in Proc. of Findings of the Association for Computational Linguistics: EMNLP 2020, pp. 884-897, Nov. 2020.
113. Pei-Hsin Wang, Sheng-Iou Hsieh, Shih-Chieh Chang, Yu-Ting Chen, Jia-Yu Pan, Wei Wei, Da-Chang Juanp "Contextual Temperature for Language Modeling," arXiv preprint arXiv:2012.13575
114. Hsin-Ping Chou, Shih-Chieh Chang, Jia-Yu Pan, Wei Wei, Da-Cheng Juan, "Remix: Rebalanced Mixup," in Proc. of ECCV 2020: Computer Vision - ECCV 2020 Workshops, pp. 95-110, Jan. 2021.
115. Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, "16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips," in IEEE International Solid-State Circuits Conference (ISSCC) 2021, pp. 250-252.
116. Jian-Wei Su, Yen-Chi Chou, Ruhui Liu;Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li,Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin S, ;Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, "15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips," in IEEE International Solid-State Circuits Conference (ISSCC), 2020, pp. 240-242.
117. Zong-Han Lee, Fu-Cheng Tsai and Shih-Chieh Chang, "Robust Binary Neural Network against Noisy Analog Computation," in Proc. of 2022 Design, Automation and Test in Europe (DATE), 2022, pp. 484-489.

(C) Books and Book Chapters

1. C.L. Lung, J.H. Chien, D.M. Kwai, and S.C Chang "Three-Dimensional Integrated Circuits Design for Thousand-Core Processors: From Aspect of Thermal Management," a chapter of the book "VLSI Design", InTech Publishing 2011 (ISBN: 979-953-307-512-8)
2. Y.G. Chen, Yiyu Shi, and S.C Chang "Live Free or Die Hard: Design for Reliability in 3D Integrated Circuit," a chapter of the book "Physical Design for 3D Integrated Circuits", CRC Press 2016 (ISBN: 978-1-4987-1036-7)